1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to, a semiconductor memory device suitable for use in a semiconductor memory device having a low power consumption state in which power consumption is lower than that in a normal operation.
2. Description of the Related Art
In semiconductor memory devices such as a DRAM (Dynamic Random Access Memory) and the like, a stabilization capacitor (decoupling capacitor) is provided between a power supply line and a ground line to suppress variation in power supply voltage, in general. It is under study that the stabilization capacitor is formed by a cell capacitor used for a memory cell of the DRAM. For instance, in Japanese Patent Application Laid-Open No. Hei10-12838 (Patent document 1), there is described a capacitance element realized with good area efficiency by arranging a plurality of cell capacitors in a mutually isolated manner.
However, since the cell capacitor of the DRAM has a low limit value (capacitor withstand voltage) with respect to an applied voltage, it is unusable as it is as a stabilization capacitor for a high-voltage power supply. Accordingly, to cope with the high-voltage power supply, the plurality of cell capacitors are connected in series between a high-voltage power supply line and the ground line to thereby divide the voltage, and a circuit giving a certain midpoint potential to connection point(s) of the cell capacitors is provided to suppress the voltage applied to each cell capacitor not to exceed the capacitor's withstand voltage. For instance, in Japanese Patent No. 3399519 (Patent document 2) and Japanese Patent Application Laid-Open No. 2006-66018 (Patent document 3), there are described stabilization capacitors formed by connecting a plurality of cell capacitors in series and keeping midpoint(s) of connection point(s) of the cell capacitors.
FIG. 8 is a view showing a configuration of the conventional semiconductor memory device provided with the stabilization capacitor formed by the plurality of cell capacitors connected in series. In FIG. 8, a circuit portion related to a power supply in the semiconductor memory device is shown.
The description will be given of a case where a low power consumption state signal DPDS is low level (hereinafter denoted by “L”), namely a case other than a low power consumption mode (Deep Power Down: DPD, also called as a power down mode) being a state in which the power consumption is reduced to lower than that in the normal operation. A booster power supply circuit 101 boosts a power supply voltage VDD supplied by a not-shown external power supply to supply a boost voltage VPP to a memory core 102.
A stabilization capacitor 104 to suppress variation in the boost voltage VPP is formed by cell capacitors C1, C2. Each of the cell capacitors C1, C2 is composed of a plurality of cell capacitors. The boost voltage VPP is supplied to a first electrode of the cell capacitor C1, a midpoint potential Vbias is supplied to the connection point of a second electrode of the cell capacitor C1 and a first electrode of the cell capacitor C2, and a second electrode of the cell capacitor C2 is grounded.
A bias generation circuit 103 controls the midpoint potential Vbias to be supplied to the connection point of the cell capacitors C1, C2. The bias generation circuit 103 detects the boost voltage VPP to control the midpoint potential Vbias so that the voltages applied to the cell capacitors C1, C2 do not exceed the capacitor withhold voltages.
Subsequently, the description will be given of a case where the low power consumption state signal DPDS is high level (hereinafter denoted by “H”), namely a case it is in the low power consumption mode. In order to reduce power consumption, the booster power supply circuit 101 stops its operation of boosting the external voltage VDD and a supply line (power supply line) of the boost voltage VPP becomes floating. In the same manner, the bias generation circuit 103 stops its operation as well, and a supply line of the midpoint potential Vbias becomes floating.
The description will be given of the operation of the conventional semiconductor memory device shown in FIG. 8 in detail with reference to FIG. 9. Hereinafter, the cell capacitors C1, C2 are assumed to have the same capacitance.
In a start-up, (time period S1), the booster power supply circuit 101 and the bias generation circuit 103 receive the low power consumption state signal DPDS of “L”. The booster power supply circuit 101 boosts the power supply voltage VDD supplied from the external power supply to boost the boost voltage VPP to be supplied to the memory core 102 to a predetermined voltage. The midpoint potentials Vbias at the cell capacitors C1, C2 composing the stabilization capacitor 104 of the boost voltage VPP become voltage-divided levels of the boost voltage VPP. Since the cell capacitors C1; C2 have the same capacitance, the midpoint potential Vbias increases in a following manner at the half (½) level of the increased voltage of the boost voltage VPP. The bias generation circuit 103 operates to make the midpoint potential Vbias be (VPP/2).
In a normal operation (time period S2), the booster power supply circuit 101 and the bias generation circuit 103 receive the low power consumption state signal DPDS of “L”. The booster power supply circuit 101 boosts the power supply voltage VDD to keep the boost voltage VPP at the predetermined voltage. The midpoint voltage of the cell capacitors C1, C2 comes to (VPP/2) being the voltage-divided boost voltage VPP, so that the bias generation circuit 103 operates to make the midpoint potential Vbias be (VPP/2).
In a low power consumption mode (time period S3), the booster power supply circuit 101 and the bias generation circuit 103 receive the low power consumption state signal DPDS of “H”. The booster power supply circuit 101 and the bias generation circuit 103 having received the low power consumption state signal DPDS of “H” stop operation to reduce the power consumption, so that the respective supply lines of the boost voltage VPP and the midpoint potential Vbias become floating. The midpoint potential Vbias of the cell capacitors C1, C2 comes to (VPP/2) being the voltage-divided boost voltage VPP.
After that, in the low power consumption mode, the boost voltage VPP gradually lowers toward the ground potential due to leak current of the memory core 102. Further, the midpoint potential Vbias gradually lowers as well at the level of (VPP/2).
In the transition from the low power consumption mode to the normal operation (time period S4) the booster power supply circuit 101 and the bias generation circuit 103 receive the low power consumption state signal DPDS of “L” to start their operations. The booster power supply circuit 101 boosts the power supply voltage VDD to increase the boost voltage VPP to the predetermined voltage. The midpoint potential Vbias of the cell capacitors C1, C2 increases in a following manner at a half (½) level of the increased voltage of the boost voltage VPP. The bias generation circuit 103 operates to make the midpoint potential Vbias be (VPP/2).
After that, when the boost voltage VPP has come to the predetermined voltage and the midpoint potential Vbias has come to (VPP/2), the normal operation starts. In this normal operation (time period S5), they operate in the same manner as in the previously described normal operation (time period S2)
In the conventional semiconductor memory devices, the midpoint potential Vbias is controlled to be kept by the bias generation circuit 103 in the start-up and normal operation. However, in the low power consumption mode, in which the bias generation circuit 103 stops and does not operate, so that the midpoint potential Vbias may come close to the boost voltage VPP as shown for example in FIG. 10. In FIG. 10, “S1” denotes the start-up and “S2” denotes the normal operation time. In addition, “S3” denotes the low power consumption time, “S4” denotes the transition from the low power consumption mode to the normal operation, and “S5” denotes the normal operation time (this applies similarly to FIG. 11, which will be described later).
After that, in the transition (S4) from the low power consumption mode to the normal operation, the booster power supply circuit 101 receives the low power consumption state signal DPDS to boost the external voltage VDD to increase the boost voltage VPP to the predetermined voltage, while the bias generation circuit 103 operates to increase the midpoint potential Vbias to (VPP/2). Therefore, the midpoint potential Vbias of the cell capacitors C1, C2 increases from the voltage in the low power consumption mode to the half (½) of the increase in the boost voltage VPP, so that the midpoint potential Vbias sometimes deviates largely from the midpoint potential Vbias at the time of the normal operation. At that time, should the voltage applied to the cell capacitor C2 come to a large voltage V1 larger than the capacitor withstand voltage, there arise problems that the cell capacitor C2 is broken, the leak current increases, and the like, affecting reliability.
Further, in the low power consumption mode, for example, the midpoint potential Vbias sometimes comes close to a ground potential as shown in FIG. 11.
After that, in the transition (S4) from the low power consumption mode to the normal operation, the booster power supply circuit 101 receives the low power consumption state signal DPDS to boost the external voltage VDD to increase the boost voltage VPP to the predetermined voltage, while the bias generation circuit 103 operates to increase the midpoint potential Vbias to (VPP/2). The midpoint potential Vbias of the cell capacitors C1, C2 increases from the voltage in the low power consumption mode to the half (½) of the increase in the boost voltage VPP, so that the midpoint potential Vbias sometimes deviates largely from the midpoint potential Vbias at the time of the normal operation. At that time, should the voltage applied to the cell capacitor C1 come to a large voltage V2 larger than the capacitor withstand voltage, there arise problems that the cell capacitor C1 is broken, the leak current increases, and the like, affecting reliability.
Thus, in the conventional semiconductor memory devices, due to the variation in the midpoint potential Vbias in the transition from the low power consumption mode to the normal operation, the voltages over the capacitor withstand voltages are sometimes applied, respectively, to the cell capacitors C1, C2 composing the stabilization capacitor 104.